The present invention relates to a digital computer and more particularly to a microprogrammable digital-processor, memory, logic, and control and addressing structure, which may be implemented in TTL logic or as a LSI (large scale integration) chip. Moreover, this invention particularly relates to an apparatus and method for handling microinstruction memory addressing in such a microprogram processor ro "routine", "subroutine", and "iterative-loop" programmatic operations.
Microinstruction processors in general may have strings of microinstructions stored in micromemory to form programs which control the sequence of information transfer within the process. Typically, a higher level operator command is implemented by a sequence of microinstructions. Micromemory addressing or microinstruction address accessing is of necessity a function of the hardware design of the processor.
Usually the micromemory is addressed by a program count register. This register, typically, is incremented after each operation to access each succeeding address in a microinstruction string. However, as the program operations to be performed become more complex, i.e., the inclusion of subroutines and iterative loops, micromemory addressing becomes more complex.
The subject improvement is to a particular type of microprogrammable unit as embodied in the teachings of Faber in patent application U.S. Ser. No. 307,863, filed Nov. 20, 1972 and assigned to the assignee of the present application. The programmable unit disclosed therein is a self-contained serial-bit by byte processor employing a soft machine architecture through microprogramming. An instruction set, at the microprogram level is provided for controlling the specific circuitry of the processor in executing basic computer operations. Essentially, the specific circuitry represents minimally committed logic or hardward which becomes committed to a specific task by control signals originating in the instruction set. Logic, control, and addressing functions are performed by circuitry which includes only those gates, registers, drivers, and related logic, which are necessary to implement the basic operations.
Such a processing unit may be comprised of five functional parts: (1) a logic unit which performs shifting, arithmetic and logic functions; (2) a microprogram memory which stores both literals and control words; (3) a memory control unit which provides the registers microprogram memory addressing; (4) a control unit which provides timing and conditional control, successor determination and instruction decoding; and (5) an external interface.
In the microprocessor, cited above, a microprogram memory (MPM) is addressed by a memory program count register (MPCR). Feeding this (MPCR) register is an alternate memory program count register (AMPCR). The AMPCR receives instructions from microprogram memory as well as from other registers within the processor.
This parent invention has a fundamental instruction set which is sufficient to perform most programmatic operations. More, but not all, sophisticated microprogram manipulations are performed by concatenation of the basic instructions. Included in the basic instruction set are STEP, SKIP, SAVE, and JUMP instructions. STEP initiates a step to the next instruction in sequence from a previous MPCR address. SKIP initiates a skip to the second next instruction in sequence from a previous MPCR address. SAVE initiates a step and a save of the current MPCR address in AMPCR. JUMP initiates a transfer of control to the AMPCR address. However, with the existing control logic the saving of a return address until a subroutine is performed for a program branch and return, or a loop within a subroutine and return, or an execution of a variable instruction external to a subroutine as part of the execution of that subroutine is not readily possible. Such operations as branch to a subroutine and return, loop within a subroutine and return and execution of an instruction external to subroutine canot be easily handled.
It is therefore an object of this invention to provide a method of data manipulation within a serial-bit by byte processor and the timing apparatus to implement this method to supply direct CALL microprogram capability.
An additional object of the invention is to similarly provide a direct GO-TO microprogram capability which does not alter the previous memory address.
Similarly, a further object of this invention is to provide an external EXECUTE command, microprogram capability.
The parent invention operates on a nine pulse operation period, the length of time needed to perform the longest arithmetic operation. The processor uses nine pulses to implement each instruction regardless of the length of time actually needed to perform the particular operation.
It is desirable to have the processor operate at the faster rate. Therefore, a further object of this invention is to provide an apparatus for adjusting the implementation period of microinstructions and for adjusting shift register lengths.